1. Field of the Invention
The present invention relates to an image sensor.
2. Description of the Related Art
In general, an image sensor is a semiconductor device for converting an optical image into an electrical signal. The image sensor may be configured as shown in FIG. 1.
With reference to FIG. 1, the related art image sensor may include a pixel unit 11, a sampling unit 12, an analog-to-digital converter (ADC) 13, a driving current supply unit 14, or the like. The pixel unit 11 may include a floating diffusion capacitor Cfd, a photo diode PD, a reset transistor Q1, a transmission transistor Q2, a source follower transistor Q3, and row selection transistor Q4. The sampling unit 12 may include a signal capacitor Cs, a reset capacitor Cr, a reset sampling transistor Q5, and a signal sampling transistor Q6. The driving current supply unit 14 may include a current transistor Q7.
The operation of the image sensor illustrated in FIG. 1 will now be described with reference to FIG. 2.
In order to sample a reset level of the pixel unit 11, the reset transistor Q1 and the reset sampling transistor Q5 are turned on. Then, a floating diffusion (FD) node is initialized, and a voltage level of an output node OUT is changed according to a voltage level of the FD node. At this time, the reset sampling transistor Q5 stores the voltage level of the output node OUT in the reset capacitor Cr.
In order to sample a signal level of the pixel unit 11, in the state in which the FD node is initialized, the reset transistor Q1 and the reset sampling transistor Q5 are turned off and the transmission transistor Q2 and the signal sampling transistor Q6 are turned on. Then, optical charges accumulated in the photo diode PD move to the FD node to change the voltage level of the output node OUT, and the signal sampling transistor Q6 stores the voltage level of the output node OUT in the signal capacitor Cs.
When signals are stored in both of the reset capacitor Cr and the signal capacitor Cs through the foregoing process, the sampling unit 12 provides a voltage difference between the reset capacitor Cr and the signal capacitor Cs to the ADC 13, thus obtaining an image signal from which reset noise has been canceled.
However, the image sensor configured and operated as described above may generate noise due to coupling of the FD node when the reset transistor Q1 and the transmission transistor Q2 operate.
In order to prevent a signal with noise from being stored in the sampling capacitors Cr and Cs, the output node OUT must be completely discharged after the operation of the reset transistor Q1 and the transmission transistor Q2, and then, a follow-up operation must be performed. Namely, the follow-up operation must be performed after securing sufficient stabilization duration (ΔSTprevious).
However, a rate of voltage drop in the output node OUT may be very slow, as compared with the FD node. Namely, as shown in FIG. 3, the voltage level of the FD node is immediately reduced as the transmission transistor Q2 is turned off, while the voltage level of the output node OUT is gradually reduced. This is because the signal capacitor Cs is connected to the output node OUT, so the discharge rate of the signal capacitor Cs affects the rate of voltage drop in the output node OUT. Also, when the amount of driving current provided by the driving current supply unit 14 is small, the driving capabilities of the source follower transistor Q3 and the row selection transistor Q4 are degraded, further lowering the rate of voltage drop in the output node OUT.
Thus, in the related art, a long stabilization duration (ΔSTprevious) must be secured due to the slow rate of voltage drop in the output node OUT, resulting in an increase in sampling time that limits the frame rate of the image sensor.